Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic are one such energy-saving that utilize reversible power. Several methodologies used previously infer the use of CMOS for reducing dissipation logic circuits. However, hardly manage maintaining their performance when it comes to fast switching networks. technology is employed overcome these difficulties, which can further scale down by charging discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic here evaluate arithmetic operations like inverter, full adder, Carry Look-Ahead adder etc. A better chance at delay digital illustrated developing Kogge-stone Adder, built using ECRL technology. The developed circuitry integrated into Fast Fourier Transform (FFT), demonstrates circuit’s enhancement DSP applications. Not only does this design reduce VLSI circuits, but also narrows minimum. This technique proved superior existing PFAL demonstrating almost 10% less minimal propagation delay. All have been simulated 45 nm Tanner EDA tool.